Many integrated circuits, such as memories, use clock signals to time and synchronize operations. Today, integrated circuits are commonly required to complete many operations within one clock period of the clock signal. For example, a “self-timed” memory may begin a read or a write access with a rising edge of a clock signal and then time the events required for the read or write access internally before the next rising edge. A static random access memory (SRAM) is a memory type that is commonly used in high speed applications and is sometimes self-timed to complete an access in one clock cycle or less. As clock speeds increase, the amount of time available to complete all of the events required for an access to an SRAM memory array is reduced.
FIG. 1 illustrates a clock timing circuit 10 for a self-timed memory in accordance with the prior art. Clock timing circuit 10 includes clock drivers 11, 13, 15, and 32, reset latch 24, write delay circuit 26, read delay circuit 28, and OR logic gate 30. Each of the clock drivers 11, 13, and 15 includes a set latch and a driver, or buffer, circuit. For example, clock driver 11 includes set latch 12 and driver 14, clock driver 13 includes latch 16 and driver 18, and clock driver 15 includes latch 20 and driver 22. Each of the latches 12, 16, 20, and 24 receives a system clock signal labeled “CLK” from, for example, a data processing system (not shown). Also, each of the latches 12, 16, 20, and 24 receives various other control signals, such as for example, an ENABLE signal, a RESET signal, a CLK_SR signal, and a WR_STROBE signal. Typically, an access to a memory (not shown) having clock timing circuit 10 begins at a rising edge of the system clock signal CLK. When the memory is accessed, a logic state of the clock signal CLK is latched in response to one or more enable signals. A chain of events required to access the memory is controlled by the clock driver circuits which represent separate clock timing paths for the memory. In clock timing circuit 10, clock driver 11 provides a timing signal labeled “CLK_ADDR_B” to latch an address for selecting one or more memory cells. Clock driver 13 provides clock signal CLK_WRITE_B to indicate whether the selected memory cells are to be written to or read from. Clock driver 15 provides clock signal CLK_DEC_B to address decoders. In the event of a read operation, clock driver 32 turns on the sense amplifiers at the appropriate time. Delay elements are used to provide the correct timing. For example, during a write operation, write delay element 26 provides write strobe WR_STROBE a predetermined delay after clock signal CLK_ADDR_B is asserted. Likewise, during a read operation, read delay element 28 provides another predetermined delay after clock signal CLK_ADDR_B is asserted before providing CLK_DEC_B and CLK_SENSE_B to the decoders and sense amplifiers, respectively. At the end of the read or write access, a feedback clock recovery signal labeled “STROBE” from the output of OR logic gate 30 to an input of reset latch 24 via a predetermined delay 29 is used to reset the latched state of the system clock signal CLK to an initial logic state in preparation for another memory access.
FIG. 2 illustrates a portion of the clock timing circuit of FIG. 1 in more detail. In FIG. 2, reset latch 20 includes NAND logic gates 36, 38, and 40, NOR logic gate 42 and driver 22. NAND logic gates 38 and 40 are cross-coupled to provide a latch 34. Driver 22 is implemented with an inverter as illustrated. Reset latch 24 includes NAND logic gates 44, 46, 52 and 48, and NOR logic gate 50. Self-timed delay 54 represents the delay provided by the combination of write delay 26, read delay 28, OR logic gate 30, and delay 29 (FIG. 1). NAND logic gates 46 and 52 provide the latching function for reset latch 24. As described above, reset latch 24 is used to reset the set latches to an initial logic state at the end of a memory access. The logic state of the clock signal CLK is held by set latch 20 until reset to the initial state by the feedback recovery signal STROBE_D (FIG. 1). Each of clock driver circuits 11 and 13 are similar to clock driver circuit 15.
A speed critical path for the clock driver circuit 15 includes a path between the clock signal CLK input of NAND logic gate 36, through latch 34 and inverter 22. When a system clock signal CLK is provided to clock driver 15 it is latched in the cross-coupled NAND logic gates 38 and 40 before being provided to the output of clock driver 15. Latching the clock signal CLK in the driver circuit of FIG. 2 adds additional gate delays to the speed critical path that may prevent the memory from meeting timing requirements for higher clock speeds. Also, having a memory with three or more independent timing paths increases clock timing complexity.
Thus, there is a need for self-timed memory with a clock timing circuit that solves the above problems.